1. Technical Field
This invention generally relates to semiconductor interconnects, and more specifically relates to an interconnection structure and method for fabricating same.
2. Background Art
A semiconductor wafer may contain an array of devices whose contacts are interconnected by patterns of metal wires. In order to take full advantage of the device and circuit density on a given wafer, it is usually necessary to make interconnections among the various devices and circuit elements in the wafer. However, due to the level of integration of devices and circuits on a wafer, interconnections can no longer be made by means of a single level network of metal lines. Often, it is necessary to form two or more such levels of metal lines which are vertically spaced apart and separated by intermediate insulators.
Electrical connections are made between the different levels of metal lines by means of interconnection structures. In its simplest form and using well known photolithographic techniques, an interconnection structure may be formed by first masking an insulator with photoresist, and then etching through a portion of the insulator to form an opening to the underlying metal layer. Once the openings are etched through the insulators separating the levels, they are filled with metal to form interconnect structures. These multiple levels of interconnection patterns of metal wires, with the individual layers connected by interconnect structures, operate to distribute signals among the circuits on the wafer.
Many semi-conductor manufacturers employ similar interconnect schemes. One of the more common implementations is to employ a vertical tungsten stud connection as a contact to the silicon device level and to form a local interconnect or xe2x80x9cMCxe2x80x9d. Subsequently, a second vertical tungsten stud connection is formed to provide electrical connection from the local interconnect to the first wiring level or metal-1. The metal-1 structure may be fabricated from copper, in order to minimize resistance and maximize device performance. Copper interconnects are most often deposited by electroplating from a liquid solution.
There can be problems with the interconnection structures described above. One such problem is created when the vertical tungsten stud structures contain porosity, often in the form of voids, seams, or cavities. These seam or voids are formed because the aspect-ratio of the feature (the ratio of depth to width) is such that the CVD tungsten deposition technique does not have sufficient conformality to fully fill these features. Often, these seams can be aggravated by wet etching or cleaning processes that are used to clean the top surface of the stud after the subsequent interconnect is patterned. The purpose of these cleaning steps is to remove contaminant materials and prepare the top surface of these tungsten stud connections so that the next level of metallization may be formed on top of the stud.
When liquid and/or gaseous contaminants are deposited into these features, they can be entrapped by the deposition of metal layers through CVD (chemical vapor deposition), PVD (physical vapor deposition), electroplating, or the like. These entrapped contaminants may subsequently cause corrosive attack, or may volatilize in high temperature operations and cause catastrophic delamination of the structure.
Accordingly, what is needed is an interconnection structure and method for fabricating same that overcomes the formation of voids during conductor fill of high aspect ratio interconnect structures and the subsequent electroplating problems that disrupt interconnection structures and electrical connections.
The preferred embodiment of the present invention provides an interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).
One advantage of the present invention is that voids or cavities in the form of open seams in the conductor layers are not formed or worsened, even with high aspect ratio structures. Preferably, a highly conformal insulator is deposited over the conductor(s). The highly conformal insulator centrally fills the interconnection structure. The highly conformal insulator is capable of filling high aspect ratio structures, recursive structures, and the like, especially with a subsequent reflow treatment after deposition of the highly conformal insulator. Moreover, the highly conformal insulator does not form the undesirable voids or cavities. There are no metal CVD or PVD depositions that are as conformal as these insulator depositions.
Another advantage of the present invention is that electroplating problems are eliminated when copper wiring is used to make the electrical connection. Specifically, because voids or cavities are avoided, the plating solution is not trapped. Therefore, when the copper is plated and during a subsequent elevated temperature anneal, no plating solution is entrapped.
Still another advantage of the present invention is that preferred interconnection structure including a central insulator filled region still maintains adequate surface area to form a viable electrical connection. Adequate electrical connection surface area preferably is maintained through conductor protrusions into an upper interconnection level. Alternatively, adequate electrical connection surface area can be maintained through an upper interconnection level protrusion to the lower conductor(s).